We know that Instructions are stored in the program memory. These instructions follow a cycle of stages to get executed when they are called. And each cycle include the following phases.
1.Fetch the instruction from memory
2.Decode the instruction.
3.Fetch data from register or port.
4.Execute the instruction.
Instruction execution takes place in two stages. And each stage require four clock cycles. The stages are :
Now let’s have a look at the 4 clock cycles of each stages.
- Clock1: Increment PC (PC <= PC+1) (phase 1)
- Clock 2,3: idle.
- Clock 4: Instruction loaded in to IR
- Clock 1 : Instruction decode
- Clock 2 : Fetch data from register or port
- Clock 3 :Operations carried out with data
- Clock 4 :Results loaded back to destination
During one instruction cycle instruction is fetched and stored in the instruction register. In the next instruction cycle, instruction is decoded and executed.
1 machine cycle= fetch + execute together
The hardware responsible for fetch and load are Program memory, instruction register, and program counter. For execution, the hardware involved are instruction decode, W register, register files, ports and ALU.
FETCH AND DECODE ARE INDEPENDENT. HENCE THEY CAN BE DONE IN PARALLEL. THIS IS CALLED PIPELINING. Pipelining increases the number of instructions that can be processed at a time. This design increase the instruction throughput (the number of instructions that can be executed in a unit of time).